Go to the source code of this file.
Macros | |
| #define | DDR_BASE 0x00000000 |
| #define | DDR_SPAN 0x3FFFFFFF |
| #define | A9_ONCHIP_BASE 0xFFFF0000 |
| #define | A9_ONCHIP_SPAN 0x0000FFFF |
| #define | SDRAM_BASE 0xC0000000 |
| #define | SDRAM_SPAN 0x03FFFFFF |
| #define | FPGA_ONCHIP_BASE 0xC8000000 |
| #define | FPGA_ONCHIP_SPAN 0x0003FFFF |
| #define | FPGA_CHAR_BASE 0xC9000000 |
| #define | FPGA_CHAR_SPAN 0x00001FFF |
| #define | LW_BRIDGE_BASE 0xFF200000 |
| #define | LEDR_BASE 0x00000000 |
| #define | HEX3_HEX0_BASE 0x00000020 |
| #define | HEX5_HEX4_BASE 0x00000030 |
| #define | SW_BASE 0x00000040 |
| #define | KEY_BASE 0x00000050 |
| #define | JP1_BASE 0x00000060 |
| #define | JP2_BASE 0x00000070 |
| #define | PS2_BASE 0x00000100 |
| #define | PS2_DUAL_BASE 0x00000108 |
| #define | JTAG_UART_BASE 0x00001000 |
| #define | JTAG_UART_2_BASE 0x00001008 |
| #define | IrDA_BASE 0x00001020 |
| #define | TIMER0_BASE 0x00002000 |
| #define | TIMER1_BASE 0x00002020 |
| #define | AV_CONFIG_BASE 0x00003000 |
| #define | PIXEL_BUF_CTRL_BASE 0x00003020 |
| #define | CHAR_BUF_CTRL_BASE 0x00003030 |
| #define | AUDIO_BASE 0x00003040 |
| #define | FIFOSPACE 1 |
| #define | LDATA 2 |
| #define | RDATA 3 |
| #define | VIDEO_IN_BASE 0x00003060 |
| #define | ADC_BASE 0x00004000 |
| #define | LW_BRIDGE_SPAN 0x00005000 |
| #define | I2C0_BASE 0xFFC04000 |
| #define | I2C0_CON 0x00000000 |
| #define | I2C0_TAR 0x00000001 |
| #define | I2C0_DATA_CMD 0x00000004 |
| #define | I2C0_FS_SCL_HCNT 0x00000007 |
| #define | I2C0_FS_SCL_LCNT 0x00000008 |
| #define | I2C0_ENABLE 0x0000001B |
| #define | I2C0_RXFLR 0x0000001E |
| #define | I2C0_ENABLE_STATUS 0x00000027 |
| #define | I2C0_SPAN 0x00000100 |
| #define | HPS_BRIDGE_BASE 0xFF700000 |
| #define | HPS_GPIO0_BASE 0x00008000 |
| #define | HPS_GPIO1_BASE 0x00009000 |
| #define | HPS_GPIO2_BASE 0x0000A000 |
| #define | I2C1_BASE 0x00505000 |
| #define | I2C2_BASE 0x00506000 |
| #define | I2C3_BASE 0x00507000 |
| #define | HPS_TIMER0_BASE 0x00508000 |
| #define | HPS_TIMER1_BASE 0x00509000 |
| #define | HPS_TIMER2_BASE 0x00600000 |
| #define | HPS_TIMER3_BASE 0x00601000 |
| #define | HPS_RSTMGR 0x00605000 |
| #define | HPS_RSTMGR_PREMODRST 0x00605014 |
| #define | FPGA_BRIDGE 0x0060501C |
| #define | HPS_BRIDGE_SPAN 0x006FFFFF |
| #define | PIN_MUX 0xFFD08400 |
| #define | CLK_MGR 0xFFD04000 |
| #define | SPIM0_BASE 0xFFF00000 |
| #define | SPIM0_SR 0x00000028 |
| #define | SPIM0_DR 0x00000060 |
| #define | SPIM0_SPAN 0x00000100 |
| #define | PERIPH_BASE 0xFFFEC000 |
| #define | MPCORE_PRIV_TIMER 0xFFFEC600 |
| #define | MPCORE_GIC_CPUIF 0xFFFEC100 |
| #define | ICCICR 0x00 |
| #define | ICCPMR 0x04 |
| #define | ICCIAR 0x0C |
| #define | ICCEOIR 0x10 |
| #define | MPCORE_GIC_DIST 0xFFFED000 |
| #define | ICDDCR 0x00 |
| #define | ICDISER 0x100 |
| #define | ICDICER 0x180 |
| #define | ICDIPTR 0x800 |
| #define | ICDICFR 0xC00 |
| #define | SYSMGR_BASE 0xFFD08000 |
| #define | SYSMGR_GENERALIO7 0x00000127 |
| #define | SYSMGR_GENERALIO8 0x00000128 |
| #define | SYSMGR_I2C0USEFPGA 0x000001C1 |
| #define | SYSMGR_SPAN 0x00000800 |
Macro Definition Documentation
◆ A9_ONCHIP_BASE
| #define A9_ONCHIP_BASE 0xFFFF0000 |
Definition at line 4 of file address_map_arm.h.
◆ A9_ONCHIP_SPAN
| #define A9_ONCHIP_SPAN 0x0000FFFF |
Definition at line 5 of file address_map_arm.h.
◆ ADC_BASE
| #define ADC_BASE 0x00004000 |
Definition at line 39 of file address_map_arm.h.
◆ AUDIO_BASE
| #define AUDIO_BASE 0x00003040 |
Definition at line 33 of file address_map_arm.h.
◆ AV_CONFIG_BASE
| #define AV_CONFIG_BASE 0x00003000 |
Definition at line 30 of file address_map_arm.h.
◆ CHAR_BUF_CTRL_BASE
| #define CHAR_BUF_CTRL_BASE 0x00003030 |
Definition at line 32 of file address_map_arm.h.
◆ CLK_MGR
| #define CLK_MGR 0xFFD04000 |
Definition at line 74 of file address_map_arm.h.
◆ DDR_BASE
| #define DDR_BASE 0x00000000 |
Definition at line 2 of file address_map_arm.h.
◆ DDR_SPAN
| #define DDR_SPAN 0x3FFFFFFF |
Definition at line 3 of file address_map_arm.h.
◆ FIFOSPACE
| #define FIFOSPACE 1 |
Definition at line 35 of file address_map_arm.h.
◆ FPGA_BRIDGE
| #define FPGA_BRIDGE 0x0060501C |
Definition at line 69 of file address_map_arm.h.
◆ FPGA_CHAR_BASE
| #define FPGA_CHAR_BASE 0xC9000000 |
Definition at line 10 of file address_map_arm.h.
◆ FPGA_CHAR_SPAN
| #define FPGA_CHAR_SPAN 0x00001FFF |
Definition at line 11 of file address_map_arm.h.
◆ FPGA_ONCHIP_BASE
| #define FPGA_ONCHIP_BASE 0xC8000000 |
Definition at line 8 of file address_map_arm.h.
◆ FPGA_ONCHIP_SPAN
| #define FPGA_ONCHIP_SPAN 0x0003FFFF |
Definition at line 9 of file address_map_arm.h.
◆ HEX3_HEX0_BASE
| #define HEX3_HEX0_BASE 0x00000020 |
Definition at line 17 of file address_map_arm.h.
◆ HEX5_HEX4_BASE
| #define HEX5_HEX4_BASE 0x00000030 |
Definition at line 18 of file address_map_arm.h.
◆ HPS_BRIDGE_BASE
| #define HPS_BRIDGE_BASE 0xFF700000 |
Definition at line 56 of file address_map_arm.h.
◆ HPS_BRIDGE_SPAN
| #define HPS_BRIDGE_SPAN 0x006FFFFF |
Definition at line 71 of file address_map_arm.h.
◆ HPS_GPIO0_BASE
| #define HPS_GPIO0_BASE 0x00008000 |
Definition at line 57 of file address_map_arm.h.
◆ HPS_GPIO1_BASE
| #define HPS_GPIO1_BASE 0x00009000 |
Definition at line 58 of file address_map_arm.h.
◆ HPS_GPIO2_BASE
| #define HPS_GPIO2_BASE 0x0000A000 |
Definition at line 59 of file address_map_arm.h.
◆ HPS_RSTMGR
| #define HPS_RSTMGR 0x00605000 |
Definition at line 67 of file address_map_arm.h.
◆ HPS_RSTMGR_PREMODRST
| #define HPS_RSTMGR_PREMODRST 0x00605014 |
Definition at line 68 of file address_map_arm.h.
◆ HPS_TIMER0_BASE
| #define HPS_TIMER0_BASE 0x00508000 |
Definition at line 63 of file address_map_arm.h.
◆ HPS_TIMER1_BASE
| #define HPS_TIMER1_BASE 0x00509000 |
Definition at line 64 of file address_map_arm.h.
◆ HPS_TIMER2_BASE
| #define HPS_TIMER2_BASE 0x00600000 |
Definition at line 65 of file address_map_arm.h.
◆ HPS_TIMER3_BASE
| #define HPS_TIMER3_BASE 0x00601000 |
Definition at line 66 of file address_map_arm.h.
◆ I2C0_BASE
| #define I2C0_BASE 0xFFC04000 |
Definition at line 44 of file address_map_arm.h.
◆ I2C0_CON
| #define I2C0_CON 0x00000000 |
Definition at line 45 of file address_map_arm.h.
◆ I2C0_DATA_CMD
| #define I2C0_DATA_CMD 0x00000004 |
Definition at line 47 of file address_map_arm.h.
◆ I2C0_ENABLE
| #define I2C0_ENABLE 0x0000001B |
Definition at line 50 of file address_map_arm.h.
◆ I2C0_ENABLE_STATUS
| #define I2C0_ENABLE_STATUS 0x00000027 |
Definition at line 52 of file address_map_arm.h.
◆ I2C0_FS_SCL_HCNT
| #define I2C0_FS_SCL_HCNT 0x00000007 |
Definition at line 48 of file address_map_arm.h.
◆ I2C0_FS_SCL_LCNT
| #define I2C0_FS_SCL_LCNT 0x00000008 |
Definition at line 49 of file address_map_arm.h.
◆ I2C0_RXFLR
| #define I2C0_RXFLR 0x0000001E |
Definition at line 51 of file address_map_arm.h.
◆ I2C0_SPAN
| #define I2C0_SPAN 0x00000100 |
Definition at line 53 of file address_map_arm.h.
◆ I2C0_TAR
| #define I2C0_TAR 0x00000001 |
Definition at line 46 of file address_map_arm.h.
◆ I2C1_BASE
| #define I2C1_BASE 0x00505000 |
Definition at line 60 of file address_map_arm.h.
◆ I2C2_BASE
| #define I2C2_BASE 0x00506000 |
Definition at line 61 of file address_map_arm.h.
◆ I2C3_BASE
| #define I2C3_BASE 0x00507000 |
Definition at line 62 of file address_map_arm.h.
◆ ICCEOIR
| #define ICCEOIR 0x10 |
Definition at line 91 of file address_map_arm.h.
◆ ICCIAR
| #define ICCIAR 0x0C |
Definition at line 90 of file address_map_arm.h.
◆ ICCICR
| #define ICCICR 0x00 |
Definition at line 88 of file address_map_arm.h.
◆ ICCPMR
| #define ICCPMR 0x04 |
Definition at line 89 of file address_map_arm.h.
◆ ICDDCR
| #define ICDDCR 0x00 |
Definition at line 94 of file address_map_arm.h.
◆ ICDICER
| #define ICDICER 0x180 |
Definition at line 96 of file address_map_arm.h.
◆ ICDICFR
| #define ICDICFR 0xC00 |
Definition at line 98 of file address_map_arm.h.
◆ ICDIPTR
| #define ICDIPTR 0x800 |
Definition at line 97 of file address_map_arm.h.
◆ ICDISER
| #define ICDISER 0x100 |
Definition at line 95 of file address_map_arm.h.
◆ IrDA_BASE
| #define IrDA_BASE 0x00001020 |
Definition at line 27 of file address_map_arm.h.
◆ JP1_BASE
| #define JP1_BASE 0x00000060 |
Definition at line 21 of file address_map_arm.h.
◆ JP2_BASE
| #define JP2_BASE 0x00000070 |
Definition at line 22 of file address_map_arm.h.
◆ JTAG_UART_2_BASE
| #define JTAG_UART_2_BASE 0x00001008 |
Definition at line 26 of file address_map_arm.h.
◆ JTAG_UART_BASE
| #define JTAG_UART_BASE 0x00001000 |
Definition at line 25 of file address_map_arm.h.
◆ KEY_BASE
| #define KEY_BASE 0x00000050 |
Definition at line 20 of file address_map_arm.h.
◆ LDATA
| #define LDATA 2 |
Definition at line 36 of file address_map_arm.h.
◆ LEDR_BASE
| #define LEDR_BASE 0x00000000 |
Definition at line 16 of file address_map_arm.h.
◆ LW_BRIDGE_BASE
| #define LW_BRIDGE_BASE 0xFF200000 |
Definition at line 14 of file address_map_arm.h.
◆ LW_BRIDGE_SPAN
| #define LW_BRIDGE_SPAN 0x00005000 |
Definition at line 41 of file address_map_arm.h.
◆ MPCORE_GIC_CPUIF
| #define MPCORE_GIC_CPUIF 0xFFFEC100 |
Definition at line 87 of file address_map_arm.h.
◆ MPCORE_GIC_DIST
| #define MPCORE_GIC_DIST 0xFFFED000 |
Definition at line 93 of file address_map_arm.h.
◆ MPCORE_PRIV_TIMER
| #define MPCORE_PRIV_TIMER 0xFFFEC600 |
Definition at line 84 of file address_map_arm.h.
◆ PERIPH_BASE
| #define PERIPH_BASE 0xFFFEC000 |
Definition at line 83 of file address_map_arm.h.
◆ PIN_MUX
| #define PIN_MUX 0xFFD08400 |
Definition at line 73 of file address_map_arm.h.
◆ PIXEL_BUF_CTRL_BASE
| #define PIXEL_BUF_CTRL_BASE 0x00003020 |
Definition at line 31 of file address_map_arm.h.
◆ PS2_BASE
| #define PS2_BASE 0x00000100 |
Definition at line 23 of file address_map_arm.h.
◆ PS2_DUAL_BASE
| #define PS2_DUAL_BASE 0x00000108 |
Definition at line 24 of file address_map_arm.h.
◆ RDATA
| #define RDATA 3 |
Definition at line 37 of file address_map_arm.h.
◆ SDRAM_BASE
| #define SDRAM_BASE 0xC0000000 |
Definition at line 6 of file address_map_arm.h.
◆ SDRAM_SPAN
| #define SDRAM_SPAN 0x03FFFFFF |
Definition at line 7 of file address_map_arm.h.
◆ SPIM0_BASE
| #define SPIM0_BASE 0xFFF00000 |
Definition at line 76 of file address_map_arm.h.
◆ SPIM0_DR
| #define SPIM0_DR 0x00000060 |
Definition at line 78 of file address_map_arm.h.
◆ SPIM0_SPAN
| #define SPIM0_SPAN 0x00000100 |
Definition at line 79 of file address_map_arm.h.
◆ SPIM0_SR
| #define SPIM0_SR 0x00000028 |
Definition at line 77 of file address_map_arm.h.
◆ SW_BASE
| #define SW_BASE 0x00000040 |
Definition at line 19 of file address_map_arm.h.
◆ SYSMGR_BASE
| #define SYSMGR_BASE 0xFFD08000 |
Definition at line 100 of file address_map_arm.h.
◆ SYSMGR_GENERALIO7
| #define SYSMGR_GENERALIO7 0x00000127 |
Definition at line 101 of file address_map_arm.h.
◆ SYSMGR_GENERALIO8
| #define SYSMGR_GENERALIO8 0x00000128 |
Definition at line 107 of file address_map_arm.h.
◆ SYSMGR_I2C0USEFPGA
| #define SYSMGR_I2C0USEFPGA 0x000001C1 |
Definition at line 113 of file address_map_arm.h.
◆ SYSMGR_SPAN
| #define SYSMGR_SPAN 0x00000800 |
Definition at line 117 of file address_map_arm.h.
◆ TIMER0_BASE
| #define TIMER0_BASE 0x00002000 |
Definition at line 28 of file address_map_arm.h.
◆ TIMER1_BASE
| #define TIMER1_BASE 0x00002020 |
Definition at line 29 of file address_map_arm.h.
◆ VIDEO_IN_BASE
| #define VIDEO_IN_BASE 0x00003060 |
Definition at line 38 of file address_map_arm.h.
